Chip Production Costs: Extra Exposure Steps Raise Price for Chinese Manufacturers
Morgan Stanley data indicates CXMT yields are one-third of Western rivals, forcing firms to accept lower output per wafer to bypass ASML's EUV restrictions.
By Natalia Costa ·
Chinese semiconductor firms are facing higher production costs as they use multiple exposure techniques on older deep ultraviolet equipment to produce advanced chips. This strategy allows manufacturers to bypass export controls that block access to extreme ultraviolet machines, but it introduces greater complexity and financial burden into the fabrication process.
The cost structure of this workaround relies on splitting complex circuit patterns into several simpler steps. Chris Mack, co-founder and CTO of Fractilia, explained that industry standards previously suggested three exposures on a 193 immersion tool matched the cost of a single EUV pass. However, he noted that at four masks, EUV becomes the more economical option. This shift means that as Chinese firms push for finer features, the price per wafer rises due to the additional time and materials required for each extra step.
Yield losses represent the most direct financial penalty of this method. Each new pattern must align precisely with previous etching, and misalignment accumulates as more layers are added. Morgan Stanley estimated in a June report that Chinese DRAM maker CXMT produces only about one-third as many bits per wafer as its Western competitors. Mack described lithography access as a hard ceiling for Chinese memory development, noting that designers often add space around features to compensate for errors, which enlarges the chip and reduces the number of usable dies from expensive wafers.
The progress achieved thus far demonstrates the viability of the DUV approach despite these drawbacks. A 2023 teardown of Huawei's Mate 60 Pro revealed that SMIC produced the Kirin 9000S processor using a second-generation 7nm-class process without EUV. More recent analysis suggests SMIC has moved its DUV-based process closer to 5nm density, although it still trails the leading processes from TSMC and Samsung. Mack cautioned that node labels alone do not reflect the full picture, stating that SMIC's N+3 process remains less scaled than established 5nm nodes from major rivals.
The long-term limit of this approach remains a subject of technical debate. Micron previously developed its 1-alpha DRAM without EUV, a feat Morgan Stanley believes CXMT can replicate for its HBM3e plans. Douglas Fuller of Copenhagen Business School expects advanced packaging to allow DUV usage for the latest DRAM generations by the end of the decade. However, Mack stated he would be hard pressed to believe 3nm or 2nm nodes could be economically viable without EUV, citing the high costs of counteracting stochastic effects with higher exposure doses.
Chinese manufacturers are not expected to halt their expansion. They can continue to push DUV limits while accepting larger dies and poorer yields. Morgan Stanley projects that CXMT will maintain its share of global DRAM bit supply, increasing from 14% in 2026 to 16% in 2028 through new greenfield capacity. The bank also anticipates that China's AI chip self-sufficiency will rise from 42% in 2025 to 70% by 2030, even as gaps in EUV technology and advanced software persist.
